1. Field of the Invention
The present invention is generally directed to transceiver applications involving transmitting and receiving parallel data. More specifically, the present invention is directed to framing parallel data generated by a receive deserializer.
2. Background
In a typical transceiver application a transmitter on one chip multiplexes parallel data, an eight bit parallel word for example, at one speed and transmits this data as serial data at a higher speed. A receiver on another chip demultiplexes the serial data and regenerates the eight bit parallel data word. However, the receiver chip has no information as to which bit of the eight bit parallel word is bit zero, the least significant bit (LSB), or which bit is bit seven, the most significant bit (MSB). Thus, information regarding the boundary of the eight bit parallel word has been lost in its transmission. The result is incorrectly framed parallel data words at the receiver which contain some bits belonging to the previous eight bit word or which contain some bits belonging to the next eight bit word.
This framing process is demonstrated generally in FIG. 1, which depicts a block diagram of a typical receiver deserializer along with a timing diagram showing how the received serial data is framed into parallel words based on a word clock. A sampling flip flop 100 receives serial data and retimes it with the rising edge of a recovered clock. The recovered clock is the source of eight phases generated by a clock generator 104. The serial data is sampled by the eight phases to generate eight bits. The eight bits are finally re-timed on one of the phases, channel word clock, to form a parallel data word. With bits B7-B0 making up the original parallel word which was serially transmitted, the timing diagram of FIG. 1 illustrates how in a typical deserializer, the received data can be incorrectly framed as a parallel data word.
Prior methods for solving this problem include the use of additional storage elements to store the last received eight bit word in order to create a new sixteen bit word from the last word and the current word. A block diagram of a deserializer which implements this prior method is shown in FIG. 2. An array of eight storage flip flops 200 is used to store a previously received eight bit word which is then combined with a currently received eight bit word. The new sixteen bit word contains a predefined data reference pattern which is transmitted upon initialization of the circuit. A comparator 202 searches through the new sixteen bit word for the predefined reference pattern and identifies the pattern location to a sixteen-to-eight multiplexer 204. The sixteen-to-eight multiplexer 204 then selects these bits as the correct eight bits to be framed with word clock and output as received data.
The timing diagram of FIG. 3 further illustrates this prior method for framing parallel data as implemented by the circuit of FIG. 2. Where bits B7-B0 represent an eight bit predefined reference pattern, the diagram indicates the combination of current and last data which forms a sixteen bit data word containing this predefined reference pattern. The bit locations of the predefined reference pattern within the sixteen bit data word are found through multiple comparisons made by the comparator 202 of FIG. 2. Once located by the comparator 202, these bit locations are selected by the multiplexer 204 as containing the correct eight bits to be framed with word clock and output as received data.
This and other prior methods of framing parallel data can present significant costs in time and materials when implementing. For example, it is apparent from the timing diagram of FIG. 3 that framing parallel data by the method presented in FIG. 2, introduces unwanted latency. There is a necessary penalty of one word clock associated with the prior method of forming a sixteen bit data word to locate the predefined eight bit reference pattern.
Additionally, increased scrutiny of the block diagram circuit of FIG. 2 indicates the complexity of the circuitry required to implement this prior method, as illustrated in FIG. 4. A circuit framework for the multiplexer 204 and comparator 202 blocks of FIG. 2 is presented in FIG. 4. Though not intended as a complete representation of these circuit blocks, the depiction in FIG. 4 shows the significant hardware required to implement the comparator 202 block of FIG. 2. Nine different sets of bit locations exist within the sixteen bit word where the predefined eight bit reference pattern might be encountered. For example, the predefined eight bit reference pattern could be located in bit locations 0-7, 1-8, 2-9, 3-10, 4-11, 5-12, 6-13, 7-14, or 8-15. It is therefore necessary to dedicate nine sets of eight comparators each to search these locations in order that the multiplexer 204 can select the correct location for framing the parallel data.
The disadvantages apparent in this and other prior methods of framing parallel data can therefore include requirements for additional data storage elements, complex comparator and multiplexer circuits, and unwanted latency inherent to these methods.
Accordingly, there exists a need for an efficient, simple and low latency method for framing the parallel data generated by a receive deserializer circuit.